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?2014 integrated device technology, inc. july 2014 dsc 3750/12 1 ? functional block diagram features: true dual-ported memory cells which allow simultaneous access of the same memory location high-speed clock to data access ? commercial: 6.5/7.5/9/12/15ns (max.) ? industrial: 12ns (max.) low-power operation ? idt70v9089/79s active: 429mw (typ.) standby: 3.3mw (typ.) ? idt70v9089/79l active: 429mw (typ.) standby: 1.32mw (typ.) flow-through or pipelined output mode on either port via the ft /pipe pin counter enable and reset features dual chip enables allow for depth expansion without additional logic full synchronous operation on both ports ? 4ns setup to clock and 1ns hold on all control, data, and address inputs ? data input, address, and control registers ? fast 6.5ns clock to data out in the pipelined output mode ? self-timed write allows fast cycle time ? 10ns cycle time, 100mhz operation in the pipelined output mode lvttl- compatible, single 3.3v (0.3v) power supply industrial temperature range (?40c to +85c) is available for selected speeds available in a 100 pin thin quad flatpack (tqfp) package green parts available, see ordering information high-speed 3.3v 64/32k x 8 synchronous dual-port static ram idt70v9089/79s/l 0 1 0/1 1 0/1 0 r/ w r oe r ce 0r ce 1r ft /pipe r i/o control memory array counter/ address reg. i/o control 3750 drw 01 a 15r (1) a 0r clk r ads r cnten r cntrst r a 0l clk l ads l a 15l (1) cnten l cntrst l counter/ address reg. r/ w l ce 0l oe l ce 1l i/o 0l -i/o 7l i/o 0r -i/o 7r , 0 1 0/1 1 0/1 0 ft /pipe l note: 1. a 15 x is a nc for idt70v9079.
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 2 description: the idt70v9089/79 is a high-speed 64/32k x 8 bit synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. pin configurations (2,3,4) notes: 1. a 15 x is a nc for idt70v9079. 2. all vcc pins must be connected to power supply. 3. all gnd pins must be connected to ground. 4. package body is approximately 14mm x 14mm x 1.4mm. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. with an input data register, the idt70v9089/79 has been opti- mized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using cmos high-performance technology, these devices typically operate on only 429mw of power. index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 idt70v9089/79pf pn100 (5) 100-pin tqfp top view (6) nc v ss ft /pipe r oe r r/ w r cntrst r ce 1r ce 0r nc nc v ss a 12r a 13r a 11r a 10r a 9r a 8r a 7r nc nc a 14r nc nc nc 3750 drw 02 nc nc ft /pipe l oe l r/ w l cntrst l ce 1l ce 0l nc nc nc v dd nc a 14l a 13l a 8l a 7l nc nc nc a 12l a 11l a 10l a 9l i/o 6r i/o 5r i/o 4r i/o 3r i/o 2r i/o 0r i/o 0l i/o il v ss i/o 2l i/o 4l i/o 5l i/o 6l i/o 7 l i/o 3l i/o 1r i/o 7r nc nc a 6r a 5r a 4r a 3r a 2r a 1r a 0r cnten r clk r ads r ads l clk l cnten l a 0l a 2l a 3l a 5l a 6l a 1l a 4l a 15r (1) a 15l (1) nc nc v dd v ss v dd gnd nc nc v ss nc nc 10/30/13
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 3 pin names truth table ii?address counter control (1,2,3) truth table i?read/write and enable control (1,2,3) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , cntrst = x. 3. oe is an asynchronous input signal. left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 15l (1) a 0r - a 15r (1) address i/o 0l - i/o 7l i/o 0r - i/o 7r data input/output clk l clk r clock ads l ads r address strobe cnten l cnten r counter enable cntrst l cntrst r counter reset ft /pipe l ft /pipe r flow-through/pipeline v dd power (3.3v) v ss ground (0v) 3750 tbl 01 oe clk ce 0 ce 1 r/ w i/o 0-7 mode x h x x high-z deselected - power down x x l x high-z deselected - power down x lh l data in write l lhhdata out read h x l h x high-z outputs disabled 3750 tbl 02 external address previous internal address internal address used clk ads cnten cntrst i/o (3) mode an x an l (4) xhd i/o (n) external address used xanan + 1 h l (5) hd i/o (n+1) counter enabled?internal address generation xan + 1an + 1 hh hd i/o (n+1) external address blocked?counter disabled (an + 1 reused) xxa 0 xx l (4) d i/o (0) counter reset to address 0 3750 tbl 03 note: 1. a 15 x is a nc for idt70v9079. notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ce 0 and oe = v il ; ce 1 and r/ w = v ih . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ads and cntrst are independent of all other signals including ce 0 and ce 1 . 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other signals including ce 0 and ce 1 . 2. lb and ub are single buffered regardless of state of ft /pipe. 3. ce o and ce 1 are single buffered when ft /pipe = v il , ce o and ce 1 are double buffered when ft /pipe = v ih , i.e. the signals take two cycles to deselect.
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 4 recommended dc operating conditions recommended operating temperature and supply voltage (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd +0.3v for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v dd + 0.3v. 3. ambient temperature under bias. chip deselected. absolute maximum ratings (1) notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (t a = +25c, f = 1.0mh z ) notes: 1. this is the parameter t a . this is the "instant on" case temperature. notes: 1. v term must not exceed v dd +0.3v. 2. v il > -1.5v for pulse width less than 10ns. grade ambient tem perature gnd v dd commercial 0 o c to +70 o c0v 3.3v + 0.3v industrial -40 o c to +85 o c0v 3.3v + 0.3v 3750 tbl 04 symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih input hig h voltag e 2.2 ____ v dd + 0.3v (1) v v il input low voltag e -0.3 (2) ____ 0.8 v 3750 tbl 05 symbol rating commercial & industrial unit v term (2) terminal voltage with respect to gnd -0.5 to +4.6 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out dc output current 50 ma 3750 tbl 06 symbol parameter (1) conditions (2 ) max. unit c in input capacitance v in = 3dv 9 pf c out (3 ) output capacitance v out = 3dv 10 pf 3750 tbl 07
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 5 notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, ta = 25c for typ, and are not production tested. i cc dc (f=0) = 90ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v dd - 0.2v ce x > v dd - 0.2v means ce 0x > v dd - 0.2v or ce 1x < 0.2v "x" represents "l" for left port or "r" for right port. 6. 'x' in part number indicates power rating (s or l). dc electrical characteristics over the operating temperature and supply voltage range (6) (v dd = 3.3v 0.3v) dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 0.3v) note: 1. at v dd < 2.0v input leakages are undefined. symbol parameter test conditions 70v9089/79s 70v9089/79l unit min. max. min. max. |i li | input leakage current (1) v dd = 3.3v, v in = 0v t o v dd ___ 10 ___ 5a |i lo | output leakage current ce 0 = v ih or ce 1 = v il , v out = 0v t o v dd ___ 10 ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 3750 tbl 08 70v9089/79x6 com'l only 70v9089/79x7 com'l only 70v9089/79x9 com'l only symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. unit i cc dynamic operating current (both ports active) ce l and ce r = v il outputs disabled f = f max (1) com'l s l 220 220 395 350 200 200 335 290 180 180 260 225 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (1) com'l s l 70 70 145 130 60 60 115 100 50 50 75 65 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (3) active port outputs disabled, f=f max (1) com'l s l 150 150 280 250 130 130 240 210 110 110 170 150 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce r and ce l > v dd - 0.2v v in > v dd - 0.2v or v in < 0.2v, f = 0 (2) com'l s l 1.0 0.4 5 3 1.0 0.4 5 3 1.0 0.4 5 3 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5) v in > v dd - 0.2v or v in < 0.2v, active port outputs disabled, f = f max (1) com'l s l 140 140 270 240 120 120 230 200 100 100 160 140 ma ind s l ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3750 tbl 09a
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 6 notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, ta = 25c for typ, and are not production tested. i cc dc (f=0) = 90ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v dd - 0.2v ce x > v dd - 0.2v means ce 0x > v dd - 0.2v or ce 1x < 0.2v "x" represents "l" for left port or "r" for right port. 6. 'x' in part number indicates power rating (s or l). dc electrical characteristics over the operating temperature and supply voltage range (6) (v dd = 3.3v 0.3v)(cont'd) 70v9089/79x12 com'l & ind 70v9089/79x15 com'l only symbol parameter test condition version typ. (4) max. typ. (4) max. unit i cc dynamic operating current (both ports active) ce l and ce r = v il outputs disabled f = f max (1) com'l s l 150 150 240 215 130 130 220 185 ma ind s l ____ 150 ____ 215 ____ ____ ____ ____ i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (1) com'l s l 40 40 65 60 30 30 55 35 ma ind s l ____ 40 ____ 60 ____ ____ ____ ____ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (3) active port outputs disabled, f=f max (1) com'l s l 100 100 160 140 90 90 150 130 ma ind s l ____ 100 ____ 150 ____ ____ ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce r and ce l > v dd - 0.2v v in > v dd - 0.2v or v in < 0.2v, f = 0 (2) com'l s l 1.0 0.4 5 3 1.0 0.4 5 3 ma ind s l ____ 0.4 ____ 3 ____ ____ ____ ____ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5) v in > v dd - 0.2v or v in < 0.2v, active port outputs disabled, f = f max (1) com'l s l 90 90 150 130 80 80 140 120 ma ind s l ____ 90 ____ 140 ____ ____ ____ ____ 3750 tbl 09b
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 7 ac test conditions figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. figure 3. typical output derating (lumped capacitive load). 3750 drw 04 590 30pf 435 3.3v data out 590 5pf* 435 3.3v data out 3750 drw 03 input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1,2 and 3 3750 tbl 10 1 2 3 4 5 6 7 8 20 40 100 60 80 120 140 160 180 200 tcd 1 , tcd 2 (typical, ns) capacitance (pf) 3750 drw 05 -1 0 10 pf is the i/o capacitance of this device, and 30pf is the ac test load capacitance ,
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 8 notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). this parameter is guaranteed by device characterization, but is not production tested. 2. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both left and right ports when ft /pipe = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v il for that port. 3. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ) and ft /pipe. ft /pipe should be treated as a dc signal, i.e. steady state during operation. 4. 'x' in part number indicates power rating (s or l). ac electrical characteristics over the operating temperature range (read and write cycle timing) (3,4) (v dd = 3.3v 0.3, t a = 0c to +70c) 70v9089/79x6 com'l only 70v9089/79x7 com'l only 70v9089/79x9 com'l only symbol parameter min.max.min.max.min.max.unit t cyc1 clock cycle time (flow-through) (2) 19 ____ 22 ____ 25 ____ ns t cyc2 clock cycle time (pipelined) (2) 10 ____ 12 ____ 15 ____ ns t ch1 clock high time (flow-through) (2) 6.5 ____ 7.5 ____ 12 ____ ns t cl1 clock low time (flow-through) (2) 6.5 ____ 7.5 ____ 12 ____ ns t ch2 clock high time (pipelined) (2) 4 ____ 5 ____ 6 ____ ns t cl2 clock low time (pipelined) (2) 4 ____ 5 ____ 6 ____ ns t r clock rise time ____ 3 ____ 3 ____ 3ns t f clock fall time ____ 3 ____ 3 ____ 3ns t sa address setup time 3.5 ____ 4 ____ 4 ____ ns t ha address hold time 0 ____ 0 ____ 1 ____ ns t sc chip enable setup time 3.5 ____ 4 ____ 4 ____ ns t hc chip enable hold time 0 ____ 0 ____ 1 ____ ns t sw r/ w setup time 3.5 ____ 4 ____ 4 ____ ns t hw r/ w hold time 0 ____ 0 ____ 1 ____ ns t sd input data setup time 3.5 ____ 4 ____ 4 ____ ns t hd input data hold time 0 ____ 0 ____ 1 ____ ns t sad ads setup time 3.5 ____ 4 ____ 4 ____ ns t had ads hold time 0 ____ 0 ____ 1 ____ ns t scn cnten setup time 3.5 ____ 4 ____ 4 ____ ns t hcn cnten hold time 0 ____ 0 ____ 1 ____ ns t srst cntrst setup time 3.5 ____ 4 ____ 4 ____ ns t hrst cntrst hold time 0 ____ 0 ____ 1 ____ ns t oe output enable to data valid ____ 6.5 ____ 7.5 ____ 9ns t olz output enable to output low-z (1) 2 ____ 2 ____ 2 ____ ns t ohz output enable to output high-z (1) 17 17 17ns t cd1 clock to data valid (flow-through) (2) ____ 15 ____ 18 ____ 20 ns t cd2 clock to data valid (pipelined) (2) ____ 6.5 ____ 7.5 ____ 9ns t dc data output hold after clock high 2 ____ 2 ____ 2 ____ ns t ckhz clock high to output high-z (1) 292929ns t cklz clock high to output low-z (1) 2 ____ 2 ____ 2 ____ ns port-to-port delay t cwdd write port clock high to read data delay ____ 24 ____ 28 ____ 35 ns t ccs clock-to-clock setup time ____ 9 ____ 10 ____ 15 ns 3750 tbl 11a
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 9 notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). this parameter is guaranteed by device characterization, but is not production tested. 2. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both left and right ports when ft /pipe = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v il for that port. 3. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ) and ft /pipe. ft /pipe should be treated as a dc signal, i.e. steady state during operation. 4. 'x' in part number indicates power rating (s or l). ac electrical characteristics over the operating temperature range (read and write cycle timing) (3,4) (v dd = 3.3v 0.3) 70v9089/79x12 com'l & ind 70v908979x15 com'l only symbol parameter min.max.min.max.unit t cyc1 clock cycle time (flow-through) (2) 30 ____ 35 ____ ns t cyc2 clock cycle time (pipelined) (2) 20 ____ 25 ____ ns t ch1 clock high time (flow-through) (2) 12 ____ 12 ____ ns t cl1 clock low time (flow-through) (2) 12 ____ 12 ____ ns t ch2 clock high time (pipelined) (2) 8 ____ 10 ____ ns t cl2 clock low time (pipelined) (2) 8 ____ 10 ____ ns t r clock rise time ____ 3 ____ 3ns t f clock fall time ____ 3 ____ 3ns t sa address setup time 4 ____ 4 ____ ns t ha address hold time 1 ____ 1 ____ ns t sc chip enable setup time 4 ____ 4 ____ ns t hc chip enable hold time 1 ____ 1 ____ ns t sw r/ w setup time 4 ____ 4 ____ ns t hw r/ w hold time 1 ____ 1 ____ ns t sd input data setup time 4 ____ 4 ____ ns t hd input data hold time 1 ____ 1 ____ ns t sad ads setup time 4 ____ 4 ____ ns t had ads hold time 1 ____ 1 ____ ns t scn cnten setup time 4 ____ 4 ____ ns t hcn cnten hold time 1 ____ 1 ____ ns t srst cntrst setup time 4 ____ 4 ____ ns t hrst cntrst hold time 1 ____ 1 ____ ns t oe output enable to data valid ____ 12 ____ 15 ns t olz output enable to output low-z (1) 2 ____ 2 ____ ns t ohz output enable to output high-z (1) 17 17ns t cd1 clock to data valid (flow-through) (2) ____ 25 ____ 30 ns t cd2 clock to data valid (pipelined) (2) ____ 12 ____ 15 ns t dc data output hold after clock high 2 ____ 2 ____ ns t ckhz clock high to output high-z (1) 2929ns t cklz clock high to output low-z (1) 2 ____ 2 ____ ns port-to-port delay t cwdd write port clock high to read data delay ____ 40 ____ 50 ns t ccs clock-to-clock setup time ____ 15 ____ 20 ns 3750 tbl 11b
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 10 an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 (4) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 3750 drw 07 (1) (1) (1) (2) t sc t hc t sw t hw t sa t ha t dc t sc t hc (5) (1 latency) timing waveform of read cycle for flow-through output ( ft /pipe "x" = v il ) (3,6) timing waveform of read cycle for pipelined output ( ft /pipe "x" = v ih ) (3,6) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ads = v il and cntrst = v ih . 4. the output is disabled (high-impedance state) by ce 0 = v ih or ce 1 = v il following the next rising edge of clock. refer to truth table 1. 5. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 6. "x" denotes left or right port. the diagram is with respect to that port. an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 3750 drw 06 (1) (1) (1) (1) (2) ce 1 (4) t sw t hw t sa t ha t dc t dc (5) t sc t hc
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 11 timing waveform of a bank select pipelined read (1,2) t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 3750 drw 08 q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 (3) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz (3) (3) t sc t hc (3) t ckhz (3) t cklz (3) t cd2 a 6 a 6 t dc t sc t hc t sc t hc notes: 1. b1 represents bank #1; b2 represents bank #2. each bank consists of one idt70v9089/79 for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w and cntrst = v ih . 3. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 4. ce 0 and ads = v il ; ce 1 and cntrst = v ih . 5. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 6. if t ccs < maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs > maximum specified, then data from right port read is not valid until t ccs + t cd1 . t cwdd does not apply in this case. timing waveform of a bank select flow-through read (6) t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 3750 drw 08a d 0 d 3 t cd1 t cklz t ckhz (1) (1) d 1 data out(b1) t ch1 t cl1 t cyc1 (1) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) d 2 d 4 t cd1 t cd1 t ckhz t dc t cd1 t cklz t sc t hc (1) t ckhz (1) t cklz (1) t cd1 a 6 a 6 t dc t sc t hc t sc t hc d 5 t cd1 t cklz (1) t ckhz (1)
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 12 data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cwdd t cd1 t dc data out "b" 3750 drw 09 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t ccs t dc t sa t sw t ha (4) (4) timing waveform port-to-port flow-through read (1,2,3,5) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. ce 0 and ads = v il ; ce 1 and cntrst = v ih . 3. oe = v il for the port "b", which is being read from. oe = v ih for the port "a", which is being written to. 4. if t ccs < maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs > maximum specified, then data from right port read is not valid until t ccs + t cd1 . t cwdd does not apply in this case. 5. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a".
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 13 r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 3750 drw 11 data out qn qn + 4 ce 1 oe t ch2 t cl2 t cyc2 t cklz (1) t cd2 t ohz (1) t cd2 t sd t hd read write read t sc t hc t sw t hw t sa t ha (4) (2) t sw t hw timing waveform of pipelined read-to-write-to-read ( oe = v il ) (3) timing waveform of pipelined read-to-write-to-read ( oe controlled) (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 3. ce 0 and ads = v il ; ce 1 and cntrst = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 3750 drw 10 qn qn + 3 data out ce 1 t cd2 t ckhz t cklz t cd2 t sc t hc t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (4) (2) (1) (1) t sw t hw write (5)
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 14 r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (4) data in dn + 2 ce 0 clk 3750 drw 13 qn data out ce 1 t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sw t hw t sa t ha read write read t cklz (2) dn + 3 t ohz (1) (1) t sw t hw oe t oe timing waveform of flow-through read-to-write-to-read ( oe = v il ) (3) timing waveform of flow-through read-to-write-to-read ( oe controlled) (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 3. ce 0 and ads = v il ; ce 1 and cntrst = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 3750 drw 12 qn data out ce 1 t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sw t hw t sa t ha read nop read t cklz (4) (2) (1) (1) t sw t hw write (5)
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 15 timing waveform of pipelined read with address counter advance (1) timing waveform of flow-through counter read with address counter advance (1) notes: 1. ce 0 and oe = v il ; ce 1 , r/ w , and cntrst = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 3750 drw 14 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 3750 drw 15 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 16 address an d 0 t ch2 t cl2 t cyc2 q 0 q 1 0 clk data in r/ w cntrst 3750 drw 17 internal (3) address ads cnten t srst t hrst t sd t hd t sw t hw counter reset write address 0 read address 0 read address 1 read address n qn an + 1 an + 2 read address n+1 data out t sa t ha 1 an an + 1 (4) (5) (6) ax t sad t had t scn t hcn (6) timing waveform of write with address counter advance (flow-through or pipelined outputs) (1) timing waveform of counter reset (pipelined outputs) (2) notes: 1. ce 0 and r/ w = v il ; ce 1 and cntrst = v ih . 2. ce 0 = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. addr0 will be ac cessed. extra cycles are shown here simply for clarification. 7. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. the ?an +1? address is written to during this cycle. address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 3750 drw 16 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 17 functional description the idt70v9089/79 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal. an asynchronous output enable is provided to ease asynchronous bus interfacing. counter enable inputs are also provided to stall the operation of the counter registers for fast interleaved memory applications. a high on ce 0 or a low on ce 1 for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70v9089/79's for depth expansion configurations. when the pipelined output mode is enabled, two cycles are required with ce 0 low and ce 1 high to re-activate the outputs. depth and width expansion the idt70v9089/79 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70v9089/79 can also be used in applications requiring expanded width, as indicated in figure 4. since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 16- bit or wider applications. 3750 drw 18 idt70v9089/79 ce 0 ce 1 v dd control inputs ce 1 ce 0 idt70v9089/79 control inputs ce 0 ce 1 a 16 /a 15 (1) ce 1 ce 0 v dd idt70v9089/79 idt70v9089/79 control inputs control inputs cntrst clk ads cnten r/ w oe , figure 4. depth and width expansion with idt70v9089/79 note: 1. a 16 is for idt70v9089. a 15 is for idt70v9079.
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ra nges 18 ordering information ordering information for flow-through devices old flow-through part new combined part 70v908s/l25 70v9089s/l12 70v908s/l30 70v9089s/l15 3750 tbl 12 idt dual-port part number dual-port i/o specitications clock specifications idt pll clock device idt non-pll clock device voltage i/o input capacitance input duty cycle requirement maximum frequency jitter to l e ra n c e 70v9089/79 3.3 lvttl 9pf 40% 100 150ps 2305 2308 2309 49fct3805 49fct3805d/e 74fct3807 74fct3807d/e 3750 tbl 14 idt clock solution for idt70v9089/79 dual-port note: 1. green parts available. for specific speeds, packages and powers contact your sales office. old flow-through part new combined part 70v907s/l25 70v9079s/l12 70v907s/l30 70v9079s/l15 3750 tbl 13 a power 99 speed a package a process/ temperature range blank i commercial (0 c to +70 c) industrial (-40 c to +85 c) pf 100-pin tqfp (pn100) 6 7 9 12 15 3750 drw 19 s l standard power low power 70v9089 70v9079 512k (64k x 8-bit) synchronous dual-port ram 256k (32k x 8-bit) synchronous dual-port ram speed in nanoseconds commercial only commercial only commercial only commercial & industrial commercial only xxxxx device type a g (1 ) green a blank 8 tube or tray tape & reel
6.42 idt70v9089/79s/l high speed 3.3v 64/32k x 8 synchronous dual-port static ram industrial and commercial temperature ran ges 19 the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com datasheet document history 01/18/99: initiated datasheet document history converted to new format cosmetic and typographical corrections added additional notes to pin configurations page 14 added depth and width expansion section. 06/11/99: page 3 deleted note 6 for table ii 11/12/99: replaced idt logo 03/31/00: combined pipelined 70v9089 family and flow-through 70v908 family offerings into one data sheet changed 200mv in waveform notes to 0mv added corresponding part chart with ordering information 01/10/01: page 3 changed information in truth table ii page 4 increased storage temperature parameters clarified t a parameter page 5 dc electrical parameters?changed wording from "open" to "disabled" removed preliminary status 01/15/04: consolidated multiple devices into one datasheet changed naming conventions from v cc to v dd and from gnd to vss removed i-temp footnote from tables page 2 added date revision to pin configuration page 4 added junctiontemperature to absolute maximum ratings table added ambient temperature footnote page 5 added i-temp numbers for 9ns speed to the dc electrical characteristics table added 6ns & 7ns speeds dc power numbers to the dc electrical characteristics table page 7 added i-temp for 9ns speed to ac electrical characteristics table added 6ns & 7ns speeds ac timing numbers to the ac electrical characteristics table page 16 added 6ns & 7ns speeds grade and 9ns i-temp to ordering information added idt clock solution table pages 1 & 17 replaced ? idt logo with tm new logo 05/11/04: pages 1 & 19 added 7ns speed grade to ordering information page 5 added 7ns speed dc power numbers to the dc electrical characteristics table page 8 added 7ns speed ac timing numbers to the ac electrical characteristics table 12/01/05: page 1 added green parts availability to features page 18 added green indicator to ordering information 01/19/09: page 18 removed "idt" from orderable part number 07/26/10: page 8 in order to correct the header notes of the ac elect chars table and align them with the industrial temp range values located in the table, the commercial t a header note has been removed pages 10-14 in order to correct the footnotes of timing diagrams, cnten has been removed to reconcile the footnotes with the cnten logic definition found in truth table ii - address counter control 07/15/14: page 1 replaced industrial 9ns with 12ns. replaced low power operation standby from 600mw (typ) to 1.32mw (typ) in the features page 2 corrected some text typos page 5 removed the 9ns industrial temp power values for the s & l offering in the dc elec chars table page 6 added the 12ns industrial temp power value for the l offering in the dc elec chars table pages 8 & 9 updated the column headings of the ac elec chars table to indicate the commercial and industrial speed grade offerings page 18 updated all the commercial and industrial speed grade offerings and added tape & reel to ordering information page 2 & 18 the label pn100-1 changed to pn100 to match the standard package code page 18 corrected old flow-through part number in table 13 to 70v907s/l25 & l30 ?

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